Metal-oxide-semiconductor field effect transistors (“MOSFETs”) implemented in power integrated circuit platforms are often referred to as “power MOSFETs.” As is well-known, the switching speed of a power MOSFET is limited by internal capacitances that occur during on-state operation of the device. One internal capacitance that can significantly affect switching speed is the gate-drain capacitance (commonly abbreviated as “Cgd” and also referred to as the “Miller capacitance”), which arises between the gate formed within the trench of the power MOSFET and the drain region located beneath the gate. To decrease the gate-drain capacitance, power MOSFETS have been introduced wherein a cavity is first formed within the semiconductor substrate between the gate and the drain region of the MOSFET and, specifically, within a doped portion of semiconductor substrate commonly referred to as the “drift space.” The cavity is filled with a material having a relatively low dielectric constant (e.g., silicon oxide or silicon nitride) to decrease the permittivity between the drain region and the later-formed gate and thus decrease the gate-drain capacitance of the completed MOSFET.
By implementing a power MOSFET in the above-described manner (i.e., wherein a cavity is formed beneath the device trench and filled with a low dielectric material), the gate-drain capacitance can be decreased and the switching speed of the device can be improved. However, any reductions in gate-drain capacitance are inherently limited by the dielectric constant of the material utilized to fill the cavity, which will necessarily be higher than the dielectric constant of air or partial vacuum. Although additional approaches have been developed to further decrease gate-drain capacitance, such as forming the device trench to have a substantially V-shaped geometry, such approaches also achieve relatively limited reductions in gate-drain capacitance.